From a sentence to a board you can actually fab.
Every board ships with its gate report. Including the parts that failed.
Brief: I want to create a board which can help me create a pet food scheduler control box. Verbatim from the pet-feeder-ctrl request, written by someone who does not design boards. Everything that follows is that same run's output.
A scroll-driven sequence of the pet-feeder-ctrl run, in 3 stages.
- Brief. A single sentence of plain-language intent.
- Placement. Every component flies from a scattered start and settles onto its own footprint.
- Board. The finished board, turning under a warm key light.
The delta
The whole capture-and-place loop, inside one working session.
One agent session took a plain-language brief through to a fully placed layout with a gate table attached, then handed it back for a human to read.
- Components on the board
- 62 components
- Nets carried through the design
- 40 nets
- PlacementNothing left in the corner of the sheet for a human to sort out.
- 62/62 placed
- Wall clock, brief to placed board
- ~2.5 h
One agent session, brief through placement, with a full gate table attached.
What we claim around those numbers is a scope claim about labour, and we have not measured it — so it arrives without a figure.

Rendered from the pet-feeder-ctrl run. Measured on a different board from the one shown here.
One qualifier before you reach the table: the run we publish — a different board — came back FAIL on its composite, because a placed board is not a signed-off board; the table, failing rows and all, is here.
What it produces
Four deliverables, and a report that grades all four.
A brief goes in, and what comes out is the set of files a fabricator, an assembler and the next engineer each need — every one of them from the run pictured beside its verdicts.
- 01
Schematic
- .kicad_sch
- .svg
A hierarchical, multi-sheet schematic: a root sheet that carries the block structure and child sheets per functional group, drawn with real library symbols and real net names rather than a flattened dump. It opens in KiCad and it prints, because the sheet is the thing another engineer will review.
Electrical rules are run strict over every sheet, and the result is reported as a number rather than as an adjective.
Child sheet s1, exported from the pet-feeder-ctrl run.
- G1ERC-zeroFAIL
37 violations over 3/3 sheets — 18 unconnected pins, 14 isolated pin labels, 5 undriven power pins. None waived.
- 02
Layout
- .kicad_pcb
- .glb
Footprints placed against the board outline and the mechanical constraints in the brief, copper poured, and the netlist carried across from the schematic rather than redrawn by hand. On one session we measured placement at 62/62 placed across 40 nets.
Then it is graded. Design rules run against the fabricator’s own rule set, on both the stored copper fill and a fresh refill.

Top side, rendered from the pet-feeder-ctrl run. Measured on a different board from the one shown here.
- G2DRC-zeroFAIL
523 violations on the stored fill and 53 with zones refilled. Both arms are required: clean in one only means a stale fill.
- G5Connectivity sanityFAIL
5 unconnected items reported by the tool against 0 unrouted nets derived from intent. The router's own count was recorded and not trusted.
- 03
Order kit
- .gbr
- .drl
- .csv
Gerbers per layer, drill files, a bill of materials, and a pick-and-place file — the packet a fabricator and an assembler actually ingest, laid out the way they expect to receive it.
The cost roll-up is a lower bound, and we label it as one. It prices the lines we can resolve to a real distributor-coded part; lines we cannot resolve are reported as unpriced instead of being filled in with a plausible guess. It is what we can price, not what you will pay.

Solder side, rendered from the pet-feeder-ctrl run.
- G7Sourcing & assemblyFAIL
Distributor codes incomplete, assembly eligibility failed, and the cost roll-up not fully priced. Code-to-part identity is never machine-verified — that line rides every cover sheet.
- 04
Bring-up doc
- .md
The document a cold reader needs to power the board for the first time: the order to bring the rails up in, the test points to sit a probe on, what each one should read, and what to do when it does not. Written for someone who was not in the session and has never seen the design.
That is not a nicety, it is a gate. The cold-reader check asks exactly one question — Can someone who has never seen this board bring it up. — and an unanswered question does not get to ride under a green table.

Detail crop, rendered from the pet-feeder-ctrl run.
- G14Cold-readerUNMEASURED
Packet and key both passed over 44 BOM rows and 3 testpoints; the graded read was not supplied. If the cold reader can't answer, the board failed regardless of DRC.
The gate report
16 gates, 3 verdicts, and one of them is neither pass nor fail.
A number nobody measured is not a pass.
Every tool in this space grades itself pass or fail. We grade out of 3, because the dangerous outcome is not the failure you can see — it is the check that never ran, quietly rendered green. When the instrument could not measure something, it says UNMEASURED and the row stays copper until somebody measures it.
- documented failure modes
- 390
- gates in the suite
- 16
- verdicts, one of them copper
- 3
Entry count for the corpus itself, and the suite it feeds. Neither is a measurement taken on pet-feeder-ctrl or on any board pictured on this page.
- PASS
- 1
- FAIL
- 9
- UNMEASURED
- 6
The composite takes the worst rung on the ladder, so one failing gate carries the whole report.
This is a real report from a real run. We did not pick a green one, and we did not drop a row. A board that arrives with 9 failing gates and 6 unmeasured ones is worth far more to the engineer who has to sign it than a board that arrives with a clean bill and no evidence — because the first one tells you exactly where to put your afternoon.
| ID | Gate | What it verifies | Verdict |
|---|---|---|---|
| G1 | ERC-zero Electrical rules across every schematic sheet, strict. Reason37 violations over 3/3 sheets — 18 unconnected pins, 14 isolated pin labels, 5 undriven power pins. None waived. | Electrical rules across every schematic sheet, strict. | FAIL |
| G2 | DRC-zero Design rules against the fab's own rule set, on both fill arms. Reason523 violations on the stored fill and 53 with zones refilled. Both arms are required: clean in one only means a stale fill. | Design rules against the fab's own rule set, on both fill arms. | FAIL |
| G3 | Netlist triangle The intent, the schematic, and the board must all agree. ReasonComponent counts agree at 44, but the board carries 4 refs the schematic does not, and 18 net names are one-sided. Compiler bugs die here, not at bring-up. | The intent, the schematic, and the board must all agree. | FAIL |
| G4 | Pin-map & package Every pin assignment checked against the part's own record. ReasonThe design instantiates no distributor-coded part, so there was nothing to check against. A subject the instrument cannot read never passes. | Every pin assignment checked against the part's own record. | UNMEASURED |
| G5 | Connectivity sanity Nothing floating, nothing undriven, nothing left unrouted. Reason5 unconnected items reported by the tool against 0 unrouted nets derived from intent. The router's own count was recorded and not trusted. | Nothing floating, nothing undriven, nothing left unrouted. | FAIL |
| G6 | Decoupling Worst-case bypass distance per power pin, not the median. Reason10.5855 mm maximum against a 7.0 mm hard limit, measured over 5 power pins. The maximum, because medians hide the worst pin. | Worst-case bypass distance per power pin, not the median. | FAIL |
| G7 | Sourcing & assembly Can this actually be bought and built, at a knowable price. ReasonDistributor codes incomplete, assembly eligibility failed, and the cost roll-up not fully priced. Code-to-part identity is never machine-verified — that line rides every cover sheet. | Can this actually be bought and built, at a knowable price. | FAIL |
| G8 | Silk & polarity Legible silkscreen, and a polarity mark you can trust at assembly. ReasonThe silkscreen stroke-width floor fired. Polarity across 6 polarized designators stayed unmeasured rather than being assumed correct. | Legible silkscreen, and a polarity mark you can trust at assembly. | FAIL |
| G9 | Assembly-side conformance Rotations and side assignments the assembler will actually use. ReasonSides within policy passed; rotation coverage was not measured. Unmeasured rotations cannot ride under a green table. | Rotations and side assignments the assembler will actually use. | UNMEASURED |
| G10 | Keepouts No copper where the design said copper must not go. Reason352 findings over the declared keepout polygons, 0 intrusions, 0 unreadable. | No copper where the design said copper must not go. | PASS |
| G11 | Power budget Rails add up under load. ReasonNo power rule ran in this invocation, so no verdict was earned. | Rails add up under load. | UNMEASURED |
| G12 | Fab preflight The order kit as the fab will receive it. Reason8 independent checks ran; rotation coverage and assembly-eligibility nulls were blockers. | The order kit as the fab will receive it. | FAIL |
| G13 | Render & viewer integrity The pictures agree with the source, not with the renderer. ReasonCrossings measured from source — 27 wires, 36 crossings on sheet, 36 markers drawn. The viewer arm had no bundle in this invocation. Claims are measured against tool output, never against a model of the renderer. | The pictures agree with the source, not with the renderer. | UNMEASURED |
| G14 | Cold-reader Can someone who has never seen this board bring it up. ReasonPacket and key both passed over 44 BOM rows and 3 testpoints; the graded read was not supplied. If the cold reader can't answer, the board failed regardless of DRC. | Can someone who has never seen this board bring it up. | UNMEASURED |
| G15 | Claims Every number in the prose traces to a field in the record. ReasonNo document was present to scan. Emptiness is reported, never assumed clean. | Every number in the prose traces to a field in the record. | UNMEASURED |
| G16 | Gate integrity The gates themselves, checked with deliberately broken fixtures. Reason15/15 broken fixtures were convicted and rows were produced for 16/16 gates — but the pristine controls for G1 and G3 drifted from their own baseline verdicts, so the suite convicted itself rather than reporting a clean meta-pass. | The gates themselves, checked with deliberately broken fixtures. | FAIL |
verdict.txt — the suite’s own plain-text output for pet-feeder-ctrl. Every verdict and every tally above is exact. The reason under each row is condensed from this file, which is the full text, byte for byte and unedited.
Milestone review
Four milestones. You read each one before the next is built on it.
A run is cut into four milestones, and each one’s artifacts land as it completes — the schematic before the layout is built on it, the layout before the order kit is built on it.
- 01
Brief
The constraints we read out of your brief, before anything is drawn.
- 02
Schematic
Parts, nets, and the electrical rule check across every sheet.
- 03
Layout
Placement and routing against the fab profile you picked.
- 04
Order kit
Gerbers, BOM, CPL, renders, and the bring-up document.
Our job is to make your signature cheap. It is not to remove it.
Reviewing a schematic you did not draw is still work. What we can do is put every constraint we read, every part we chose, and every verdict we earned in front of you in the order you would have checked them anyway — so the review is reading a decision record rather than re-deriving one.
What we will not do is call the board done on your behalf. You are the engineer of record. That is not a disclaimer, it is the design.
Nothing pauses a run to wait for your signature.
Runs are not held for a signature yet — the four milestones land in order and each is readable before the next is built on it.
So the ladder above is a reading order, not a set of locks. A run that starts runs through to its stop — the order kit, or the milestone it could not clear — and you read each stage as it lands instead of all of it at the end. A blocking approval gate is work we intend to do. Until it exists, this panel says so rather than letting the rest of the page imply otherwise.
None of that changes what gets checked. When a run’s worker attaches a verdict table, it is the same 16 gates, reported whether the row passed, failed, or went unmeasured.
Pricing
Every plan prints which layer counts are proven.
Credits buy synthesis runs. The number a pricing page usually oversells — layer count — is printed twice on every card: what we have taken through the gates, and what is still in progress. Nothing moves from the second line to the first until the gates say it can.
Free
$0no card
- Proven
- 2 layers
- In progress
- none claimed
- Credits
- 10/mo
Enough to run a real board end to end and read the gate report yourself.
- 10 synthesis credits a month
- 2-layer boards
- Full 16-gate report on every run
- Gerbers, drill, BOM, CPL
- Community support
Starter
$29/mo
- Proven
- 2–4 layers
- In progress
- none claimed
- Credits
- 60/mo
The whole proven envelope, for people shipping hardware this quarter.
- 60 synthesis credits a month
- 2 and 4-layer boards
- Milestone review at brief, schematic, layout, and kit
- 3D board model and renders
- Bring-up document with every kit
- Priority queue
Creator
Recommended$79/mo
- Proven
- 2–4 layers
- In progress
- 6 layers
- Credits
- 180/mo
For teams running several boards at once, with room to grow past 4 layers.
- 180 synthesis credits a month
- 2 and 4-layer boards
- 6-layer in progress — you get it when it clears the gates
- Impedance-controlled routing constraints
- Dedicated queue allocation
- Direct email support
Studio
$199/mo
- Proven
- 2–4 layers
- In progress
- 6 layers and larger
- Credits
- 500/mo
For production teams who need custom fab rules and a queue of their own.
- 500 synthesis credits a month
- 2 and 4-layer boards
- 6-layer and larger in progress — shipped as each clears the gates
- Custom design rule packages
- Dedicated worker pool
- Priority support
Checkout runs inside the app, on the billing page, once you have an account. Plans bill monthly and can be changed there.
Top-ups
- Starter Pack50 credits$15
- Pro Pack150 credits$39
- Mega Pack500 credits$99
Credits are spent per run, and a run’s cost is set by the board you ask for — layer count drives it, and the price rises with the stackup, not with a subscription tier. The exact figure is on screen before you spend a credit.
Questions
The questions an EE asks before trusting a tool.
Do I still have to review the output?
What happens when a gate fails?
You get the board and the table that convicted it. The run whose artifacts ship on this page carries a composite verdict of FAIL — 1 pass, 9 fail, 6 unmeasured across 16 gates — and every artifact from it is still here, including a board that is placed and carries copper but is not cleanly routed. Each failing row prints the reason the suite recorded, so you know where to put your afternoon. Nothing is hidden and nothing is quietly re-run until the table looks green.
The reasons in the gate table further up this page are condensed from that run’s own text so they fit a column. The file they were condensed from is published untouched:
Does every board come with a gate report?
A board comes with the verdict table its own run produced. Where the gate suite ran, the report is an artifact of that run and downloads with the kit. Where it did not, the board says no verdict table attached to this run in copper, and leaves it at that. A board never inherits another board’s rows, and it never shows a green tick nothing earned.
The 16-row table on this page is one specific run’s, named and linked, and it is here as evidence of what the suite produces rather than as a description of the board you have not run yet.
What does UNMEASURED mean, and why not just call it a pass?
What does Lithance not do yet?
The envelope is the whole answer, so it is stated before you ask where it is: an engineer who cannot find your limit assumes you are hiding it.
- Layer countProven, and shipped with a gate report attached.
- 2–4 layers
- Board complexityPer board, in a single run.
- up to ~100 components
- Beyond thatBeing built. Not being sold.
- 6-layer and larger are in progress
In progress means exactly that: it is not proven, so it is not sold as if it were, and it is not set in the typeface this page reserves for measured values. The envelope widens when the gates say it can, not when a pricing page needs it to.
An instrument that will not state its range is not an instrument.
What happens when a board falls outside the envelope?
The run stops and names the limit it hit — you hear that from us, up front, not from a fab and not from a bench. The panel below is that stop in the product’s own treatment.
Run stopped
envelope exceededThis board is outside the proven envelope
The design needs more layers or more components than we can stand behind today. We would rather stop than hand you a board we cannot vouch for.
- What to do
- Reduce the layer count or the part count, or split the design across boards.
Excerpt, not a screenshot: these three fields are the strings a real run renders at this limit, read from the same failure-copy module the product reads. The live panel also returns your credits and links back into your brief, which needs a job this page does not have. This stop is non-retryable, so the product sends you back to edit the brief.
Which files do I get, and can I open them without Lithance?
The kit is the schematic as a PDF, gerbers and Excellon drill as a ZIP, the bill of materials and the pick-and-place as CSV, the populated board as a GLB, top and bottom renders, and the constraint read-out the run took from your brief. Where the run produced them, the gate report and the bring-up document download with the rest.
What is not in that list is a KiCad project. There is no .kicad_sch and no .kicad_pcb in the kit, and Lithance does not parse or view KiCad files in the browser. What does ship is fab-standard: gerbers, drill, BOM and CPL are the interchange every fabricator and every EDA package already reads. There is no proprietary format and no plugin to install, so nothing in the kit stops working the day you stop paying us.
Does a run stop and wait for me at each milestone?
Not today. Runs are not held for a signature yet — the four milestones land in order and each is readable before the next is built on it.
So brief, schematic, layout and kit are real divisions of the work rather than labels on a progress bar: the schematic is readable before the layout is built on it, and the layout before the kit is built on it. What does not exist yet is a blocking approval gate — nothing pauses to collect a signature — and we are not going to describe one as though it did.
Who owns the output?
What happens if a run fails?
Gate tallies above are from the pet-feeder-ctrl run. Every render, schematic, model, and gate row on this page is from this one run. They describe that board, not yours.
